1. Field of the Invention
This invention relates generally to data registers in microprocessor circuitry and more particularly to a Single Instruction Multiple Data (SIMD) correction circuit for modifying the results of an arithmetic/shift operation.
2. Description of Related Art
Heretofore, logic circuits have been proposed to improve performance of arithmetic/shift operations in data processing. With the increasing need for processing large amounts of data at ever increasing speed, improved efficiency of arithmetic/shift operations is very important. In particular, one of the difficulties of Multi-media, especially relating to graphics, is the large number of data that must be processed. An attribute of the Single Instruction Multiple Data (SIMD) is that each SIMD instruction can perform an operation on each 8 bit, 16 bit, 32 bit, or 64 bit field of a 64 bit operand independently.
A SIMD ADD, for example, would perform an add on the first, second, third and fourth 16 bit section of the register operands as if the SIMD ADD were 4 independent 16 bit add instructions. A SIMD SHIFT, for example, would perform a shift on the first, second, third, and fourth 16 bit section of the register operands as if the SIMD SHIFT were 4 independent 16 bit SHIFT instructions. Also, the SHIFT operations include shift left, shift right logical, shift right arithmetic.
SIMD has gained recent popularity with the announcement of the Intel MMX Extension. The MMX is a SIMD architecture. Implementing MMX extensions to the X86 architecture costs additional execution units dedicated to the MMX format. Converting a standard execution unit to perform both standard and SIMD operations introduces difficulties that have not heretofor been addressed. First, additional execution units adds delay to critical paths such as carry propagate paths since in SIMD the carry between SIMD sub-operands (16 bit or 32 bit sections) must be suppressed. Second, additional execution units requires additional silicon real estate (area). Third, additional execution units increases the development time and cost because the execution units are highly specialized circuits.